On the Design of SET Adders
نویسندگان
چکیده
Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG’s). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive– input SET TLG’s for building the adder. The paper also presents design details and characteristics (delay and power dissipation) of a 16-bit Kogge-Stone SET adder.
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